The present invention relates to an improved digital signal processing apparatus (hereinafter referred to as “DSP”).
In Japanese Patent Application Laid-open Publication No. 2000-057112, for example, it is disclosed that clock pulses are supplied to an arithmetic operation section, including a multiplier, adder, resister, etc., only during a period when a DSP is executing an arithmetic instruction, and that the clock supply to the arithmetic processing section is stopped to deactivate the arithmetic processing section during another period when the DSP is not executing an arithmetic instruction and thereby reduce power consumption by the DSP (see particularly paragraph [0031] and FIG. 4 of the No. 2000-057112 publication).
With the DSP disclosed in the No. 2000-057112 publication, clock pulses would be supplied to various components of the arithmetic operation section throughout a period when the DSP is performing arithmetic operations, irrespective of the content of the arithmetic operations, as along as the arithmetic operations concern a process requested from outside the DSP. However, in a case where a multiplication result of two numeric value data is retained in a register, and if values of the lower four bits of one of the two numeric value data to be multiplied are all zero (0), for example, all values of the lower four bits of the multiplication result too will be “0”. In such a case, further power consumption reduction will be achieved if the clock pulse supply to flip-flops for retaining the values of the lower four bits can be stopped.